A transistor for high power purposes that can handle electric power of several watts or over is called a power transistor. Of such power transistors, a power MISFET includes a longitudinal type and a horizontal type, and may be classified as a trench (groove) gate type and a planar gate type, depending on the gate structure.
The need to prevent the breakdown of a gate oxide film is known. For instance, in a trench gate-type power MISFET formed on a semiconductor substrate, and having an n−-type epitaxial layer, an n+-epitaxial layer, and a p-type epitaxial layer stacked successively, a gate electrode layer formed within a groove that is formed through the p-type epitaxial layer and the n+-type epitaxial layer and that reaches the n−-type epitaxial layer, and an n-type thin film semiconductor layer formed at side surfaces of the groove, a pn+n− diode is formed with use of the p-type epitaxial layer, the n+-type epitaxial layer, and the n−-type epitaxial layer. In this arrangement, the impurity concentration and thickness of the n+-type epitaxial layer are controlled so that the breakdown voltage of the pn+n− diode is lower than that of the surface of a gate oxide provided at the bottom of the groove. As a result, the pn+n− diode could be subject to avalanche breakdown more readily than the surface of the gate oxide film, thereby preventing the breakdown of the gate oxide film. Such an arrangement is taught, for example, in Japanese Unexamined Patent Publication No. Hei 10 (1998)-308512.
Further, there is known another technique of improving dielectric breakdown of a trench gate-type power MISFET including a channel forming layer on the upper surface of a semiconductor substrate. In that MISFET, a source region is provided at a surface layer portion of the channel forming layer, and a groove is provided at the center of the source region so as to reach the drain region, and a gate electrode is provided on the inner walls of the groove. In this technique, the gate oxide film is locally made thick, thereby permitting the concentration of an electric field at the corner portions of the groove bottom to be mitigated to provide for the improvement of dielectric breakdown. Such a technique is disclosed, for example, in Japanese Unexamined Patent Publication No. Hei 01 (1989)-192175.